ഫലകം:Infobox CPU architecture/doc

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This template is for CPU architectures.

Usage[തിരുത്തുക]

{{Infobox CPU architecture
| name       = 
| designer   = 
| bits       = 
| introduced = 
| version    = 
| design     = 
| type       = 
| encoding   = 
| branching  = 
| endianness = 
| page size  = 
| extensions = 
| open       = 
| registers  = 
| gpr        = 
| fpr        = 
}}

Description[തിരുത്തുക]

{{Infobox CPU architecture
| name       = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
| designer   = Designer of the architecture
| bits       = Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
| introduced = Year introduced
| version    = Version/revision of architecture/ISA
| design     = Design strategy, e.g. RISC, CISC
| type       = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
| encoding   = Instruction set encoding, e.g. Fixed or Variable
| branching  = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
| endianness = Byte ordering, i.e. Little, Big, Bi
| page size  = Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
| open       = Is the architecture open or not? (as in free or proprietary)
| registers  = Number and size of processor registers 
| gpr        = Number of general-purpose registers (and size, if not indicated by bits=)
| fpr        = Number of floating-point registers (and size, if not indicated by bits=)
}}

All fields are optional.

Example[തിരുത്തുക]

SPARC
രൂപകൽപ്പനSun Microsystems
ബിറ്റുകൾ64-bit (32 → 64)
മാർക്കറ്റിലിറക്കിയത്1985
പതിപ്പ്V9 (1993)
ഡിസൈൻRISC
തരംRegister-Register
എൻകോഡിങ്Fixed
ബ്രാഞ്ചിങ്Condition code
എൻഡിയൻനെസ്Bi (Big → Bi)
പേജ് സൈസ്8 KiB
എക്സ്റ്റെൻഷനുകൾVIS 1.0, 2.0, 3.0
OpenYes
രജിസ്റ്ററുകൾ
ജനറൽ പർപ്പസ്31 (G0 = 0; non-global registers use register windows)
ഫ്ലോട്ടിങ് പോയിന്റ്32
{{Infobox CPU architecture
| name       = SPARC
| designer   = [[Sun Microsystems]]
| bits       = 64-bit (32 → 64)
| introduced = 1985
| version    = V9 (1993)
| design     = RISC
| type       = Register-Register
| encoding   = Fixed
| branching  = Condition code
| endianness = Bi (Big → Bi)
| page size  = 8 KiB
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
| open       = Yes
| gpr        = 31 (G0 = 0; non-global registers use [[register window]]s)
| fpr        = 32
}}

Parameters[തിരുത്തുക]

All parameters are optional.

name
Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
designer
Designer of the architecture
bits
Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
introduced
Year introduced
version
Version/revision of architecture/ISA
design
Design strategy, e.g. RISC, CISC
type
Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
encoding
Instruction set encoding, e.g. Fixed or Variable
branching
Branching evaluation, e.g. Condition register, Condition code, Compare and branch
endianness
Byte ordering, i.e. Little, Big, Bi
page size
Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
extensions
ISA extensions, i.e. MMX, SSE, AltiVec, etc
open
Is the architecture open or not? (as in free or proprietary)
registers
Number and size of processor registers
gpr
Number of general-purpose registers (and size, if not indicated by bits=)
fpr
Number of floating-point registers (and size, if not indicated by bits=)

See also[തിരുത്തുക]


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